Distributed memory computing systems, such as multi-processor (MP) systems, may have a distributed shared memory interconnect architecture. In these multi-processor systems, the task of maintaining memory coherency is frequently divided between the logic of two or more system agents. Logic of a first agent, which may be referred to as a home agent, may be responsible for managing a portion of system memory. The home agent logic may also be responsible for returning data to cache agents, alternatively referred to as caching agents, resolving conflicts between caching agents, and processing memory routines which maintain proper memory order. Logic of caching agents may be responsible for providing responses and supplying data for snoops from other system agents. Additionally, the caching agents may be responsible for providing data, with the correct cache state, to underlying processor caches.
One style or method of design for implementing home agent logic is referred to as a conflict address match (CAM) design. During operation, the home agent logic of CAM-based designs may compare the full physical addresses (PA) for incoming memory requests with full physical addresses for transactions which the home agent has already received. By performing comparisons using full physical addresses, the home agents can detect conflicts between transactions. Unfortunately, CAM-based designs present system designers with multiple implementation challenges as the number of processors increases in multi-processor (MP) systems. One problem stems from the fact that certain memory transactions do not send and/or receive full physical addresses in the MP systems. Other problems arise as the number of tracking elements and the required physical address size increase in the MP systems. As the number of tracking elements increases, as well as when the PA size increases, the MP systems often present problems related to required silicon implementation area, timing, and convergence.
There are no existing mechanisms which implement home agent logic so that the logic can adequately support the use of partial physical addresses. Consequently, logic designed for existing CAM-based home agents cannot generally accommodate MP systems while using a partial PA. Additionally, timing and convergence issues continue to pose problems for system designers when they implement MP systems which use a full PA for all memory transactions.